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Features
* Programmable 16,777,216 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
* 3.3V Output Capability * 5V Tolerant I/O Pins * Program Support using the Atmel ATDH2200E System or Industry Third-party * * *
Programmers In-System Programmable (ISP) via 2-wire Bus Simple Interface to SRAM FPGAs Compatible with Atmel AT40K and AT94K Devices, Altera(R) FLEX(R), APEXTM Devices, Lucent(R) ORCA(R) FPGAs, Xilinx(R) XC3000, XC4000, XC5200, Spartan(R), Virtex(R) FPGAs, Motorola(R) MPA1000 FPGAs Cascadable Read-back to Support Additional Configurations or Higher-density Arrays Low-power CMOS FLASH Process Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC Footprint Packages), 20-lead PLCC and 44-lead TQFP Packages Emulation of Atmel's AT24CXXX Serial EEPROMs Low-power Standby Mode Single Device Capable of Holding 4-bit Stream Files Allowing Simple System Reconfiguration Fast Serial Download Speeds up to 33 MHz Endurance: 10,000 Write Cycles Typical Green (Pb/Halide-free/RoHS Compliant) Package Options Available
* * * * * * * * *
FPGA Configuration Flash Memory AT17F16
1. Description
The AT17F Series of In-System Programmable Configuration PROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The AT17F Series device is packaged in the 8-lead LAP, 20-lead PLCC and 44-lead TQFP, see Table 1-1. The AT17F Series Configurator uses a simple serial-access procedure to configure one or more FPGA devices. The AT17F Series Configurators can be programmed with industry-standard programmers, Atmel's ATDH2200E Programming Kit or Atmel's ATDH2225 ISP Cable.
Table 1-1.
Package 8-lead LAP 20-lead PLCC 44-lead TQFP
AT17F Series Packages
AT17F16 Yes Yes Yes
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2. Pin Configuration
8-lead LAP
DATA CLK RESET/OE CE 1 2 3 4 8 7 6 5 VCC SER_EN CEO (A2) GND
20-lead PLCC
NC DATA NC VCC NC 3 2 1 20 19 NC GND PAGESEL0 NC NC 9 10 11 12 13 CLK NC RESET/OE PAGESEL1 CE 4 5 6 7 8 18 17 16 15 14 NC SER_EN PAGE_EN READY CEO (A2)
44 TQFP
NC CLK NC NC DATA PAGE_EN VCC NC NC SER_EN NC 44 43 42 41 40 39 38 37 36 35 34
NC NC NC NC NC NC NC NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
NC NC NC NC NC NC NC NC NC NC READY
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NC RESET/OE PAGESEL0 CE NC NC GND PAGESEL1 NC CEO(A2) NC
AT17F16
3. Block Diagram
READY
Power-on Reset
Reset
Clock/Oscillator Logic
CLK
PAGE_EN PAGESEL0 PAGESEL1
Config. Page Select
CEO(A2) Serial Download Logic
2-wire Serial Programming
DATA
Flash Memory
CE/WE/OE Data Address
CE Control Logic RESET/OE SER_EN
4. Device Description
The control signals for the configuration memory device (CE, RESET/OE and CLK) interface directly with the FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data from the configuration device without requiring an external intelligent controller. The RESET/OE and CE pins control the tri-state buffer on the DATA output pin and enable the address counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its DATA pin. The CE pin also controls the output of the AT17F Series Configurator. If CE is held High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE. When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
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5. Pin Description
Table 5-1. Pin Description
AT17F16 Name DATA CLK PAGE_EN PAGESEL0 PAGESEL1 RESET/OE CE GND CEO A2 READY SER_EN VCC I/O I/O I I I I I I - O 6 I O I - - 7 8 15 17 20 23 35 38 14 21 8 LAP 1 2 - - - 3 4 5 20 PLCC 2 4 16 11 7 6 8 10 44 TQFP 40 43 39 14 19 13 15 18
5.1
DATA(1)
Three-state DATA output for configuration. Open-collector bi-directional pin for programming.
5.2
CLK(1)
Clock input. Used to increment the internal address and bit counter for reading and programming.
5.3
PAGE_EN(2)
Input used to enable page download mode. When PAGE_EN is high the configuration download address space is partitioned into 4 equal pages. This gives users the ability to easily store and retrieve multiple configuration bitstreams from a single configuration device. This input works in conjunction with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is Low (ISP mode) this pin has no effect.
Notes:
1. This pin has an internal 20 k pull-up resistor. 2. This pin has an internal 30 k pull-down resistor.
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AT17F16
5.4 PAGESEL[1:0](2)
Page select inputs. Used to determine which of the 4 memory pages are targeted during a serial configuration download. The address space for each of the pages is shown in Table 5-2. When SER_EN is Low (ISP mode) these pins have no effect. Table 5-2. Address Space
AT17F16 (16 Mbits) 00000 - 3FFFFh 40000 - 7FFFFh 80000 - BFFFFh C0000 - FFFFFh 00000 - FFFFFh
Paging Decodes PAGESEL = 00, PAGE_EN = 1 PAGESEL = 01, PAGE_EN = 1 PAGESEL = 10, PAGE_EN = 1 PAGESEL = 11, PAGE_EN = 1 PAGESEL = XX, PAGE_EN = 0
5.5
RESET/OE(1)
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low level on RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data output driver.
5.6
CE(1)
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the address counter and enables the data output driver. A High level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
5.7
GND
Ground pin. A 0.2 F decoupling capacitor between VCC and GND is recommended.
5.8
CEO
Chip Enable Output (when SER_EN is High). This output goes Low when the internal address counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the 4 partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address maximum value is the highest address in the device, see Table 5-2 on page 5. In a daisy chain of AT17F Series devices, the CEO pin of one device must be connected to the CE input of the next device in the chain. It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay High until the entire EEPROM is read again.
5.9
A2(1)
Device selection input, (when SER_EN Low). The input is used to enable (or chip select) the device during programming (i.e., when SER_EN is Low). Refer to the AT17F Programming Specification available on the Atmel web site for additional details.
Notes:
1. This pin has an internal 20 k pull-up resistor. 2. This pin has an internal 30 k pull-down resistor.
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5.10
READY
Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (recommended 4.7 k pull-up on this pin if used).
5.11
SER_EN(1)
The serial enable input must remain High during FPGA configuration operations. Bringing SER_EN Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be tied to VCC.
5.12
VCC
+3.3V (10%).
Notes:
1. This pin has an internal 20 k pull-up resistor. 2. This pin has an internal 30 k pull-down resistor.
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AT17F16
6. FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory. The AT17F Serial Configuration PROM has been designed for compatibility with the Master Serial mode. This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.
7. Control of Configuration
Most connections between the FPGA device and the AT17F Serial Configurator PROM are simple and self-explanatory. * The DATA output of the AT17F Series Configurator drives DIN of the FPGA devices. * The master FPGA CCLK output drives the CLK input of the AT17F Series Configurator. * The CEO output of any AT17F Series Configurator drives the CE input of the next Configurator in a cascade chain of configurator devices. * SER_EN must be connected to VCC or allowed to float to logic High via the internal pull-up resistor (except during ISP). * The READY pin is available as an open-collector indicator of the device's reset status; it is driven Low while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete. * PAGE_EN must be held Low if download paging is not desired. The PAGESEL[1:0] inputs must be tied off High or Low. If paging is desired, PAGE_EN must be High and the PAGESEL pins must be set to High or Low such that the desired page is selected, see Table 5-2 on page 5.
8. Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories, cascaded configurators provide additional memory. After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE on each configurator is driven to its active (Low) level. If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive (High) level.
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9. Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the 2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated inside the chip. The AT17F parts are read/write at 3.3V nominal. Refer to the AT17F Programming Specification available on the Atmel web site (www.atmel.com) for more programming details. AT17F devices are supported by the Atmel ATDH2200E programming system along with many third party programmers.
10. Standby Mode
The AT17F Series Configurators enter a low-power standby mode whenever SER_EN is High and CE is asserted High. In this mode, the AT17F Configurator consumes less than 5 mA of current at 3.6V. The output remains in a high-impedance state regardless of the state of the OE input.
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11. Absolute Maximum Ratings*
Operating Temperature................................... -40 C to +85 C Storage Temperature .................................... -65 C to +150 C Voltage on Any Pin with Respect to Ground ..............................-0.1V to VCC +0.5V Supply Voltage (VCC) .........................................-0.5V to +4.0V Maximum Soldering Temp. (10 sec. @ 1/16 in.)............ 260 C ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
12. Operating Conditions
AT17F Series Configurator Symbol Description Commercial VCC Industrial Supply voltage relative to GND -0 C to +70 C Supply voltage relative to GND -40 C to +85 C Min 2.97 2.97 Max 3.63 3.63 Units V V
13. DC Characteristics
AT17F16 Symbol VIH VIL VOH VOL VOH VOL ICCA IL ICCS Description High-level Input Voltage Low-level Input Voltage High-level Output Voltage (IOH = -2.5 mA) Low-level Output Voltage (IOL = +3 mA) High-level Output Voltage (IOH = -2 mA) Low-level Output Voltage (IOL = +3 mA) Supply Current, Active Mode (3.6V 33 MHz) Input or Output Leakage Current (VIN = VCC or GND) Commercial Supply Current, Standby Mode Industrial 2 mA -10 2.4 Industrial 0.4 40 10 2 V mA A mA Commercial 0.4 V V Min 2.0 0 2.4 Max VCC 0.8 Units V V V
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14. AC Characteristics
CE TSCE RESET/OE TLC CLK TOE TCE DATA TOH TCAC TOH TDF THC THOE TSCE THCE
15. AC Characteristics when Cascading
RESET/OE
CE
CLK TCDF DATA
LAST BIT FIRST BIT
TOCK CEO
TOCE
TOOE
TOCE
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AT17F16
16. AC Characteristics
AT17F16 Symbol TOE(2) TCE(2) TCAC(2) Description Commercial OE to Data Delay Industrial CE to Data Delay
(1)
Min
Typ
Max 50 55 55 60
Units ns ns ns ns ns ns ns ns
Commercial Industrial(1) Commercial CLK to Data Delay Industrial Data Hold from CE, OE, or CLK
(1)
3
30 30
Commercial TOH TDF(3) Industrial CE or OE to Data Float Delay
(1)
0 0 15 15 15 15 15 15 20 25 0 0 20 20 10 10 33 33 12 12 25 25
Commercial Industrial CLK Low Time
(1)
ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz MHz s s s s
Commercial TLC Industrial CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) RESET/OE Low Time (guarantees counter is reset) Maximum Input Clock Frequency SEREN = 0 Maximum Input Clock Frequency SEREN = 1 Write Cycle Time(4)
(1)
Commercial THC Industrial
(1)
Commercial Industrial(1) Commercial Industrial
(1)
TSCE
THCE
Commercial Industrial(1) Commercial Industrial
(1)
THOE
FMAX
Commercial Industrial
(1)
FMAX
Commercial Industrial
(1)
TWR
TEC Notes:
Erase Cycle Time(4)
Commercial Industrial
(1)
1. Preliminary specifications for military operating range only. 2. AC test lead = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels. 4. See the AT17F Programming Specification for procedural information.
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16.1
AC Characteristics When Cascading
AT17F16 Description Commercial CLK to Data Float Delay Industrial Commercial CLK to CEO Delay Industrial Commercial CE to CEO Delay Industrial Commercial RESET/OE to CEO Delay Industrial Commercial Maximum Input Clock Frequency Industrial 1. AC test lead = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels. 33 MHz 35 33 ns MHz 40 35 ns ns 55 35 ns ns 50 50 ns ns Min Max 50 Units ns
Symbol TCDF(3) TOCK(2) TOCE(2) TOOE(2)
FMAX Notes:
17. Thermal Resistance Coefficients
Package Type 8CN4 Leadless Array Package (LAP) JC [ C/W] JA [ C/W]
(1)
AT17F16 - - - - 17 62
20J
Plastic Leaded Chip Carrier (PLCC)
JC [ C/W] JA [ C/W](1) JC [ C/W] JA [ C/W]
(1)
44A
Thin Plastic Quad Flat Package (TQFP)
Note:
1. Airflow = 0 ft/min.
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AT17F16
18. Ordering Information
Memory Size Ordering Code AT17F16-30TQC 16-Mbit AT17F16-30TQI Notes: 44A - 44 TQFP Package(1)(2) 44A - 44 TQFP Operation Range Commercial (0 C to 70 C) Industrial (-40 C to 85 C)
1. For the -30BJC and -30BJI packages, customers may migrate to the AT17F32-BJU. 2. For the -30JC and -30JI packages, customers may migrate to the AT17F16-30JU.
19. Green Package Options (Pb/Halide-free/RoHS Compliant)
Memory Size 16-Mbit Ordering Code AT17F16-30CU AT17F16-30JU Package 8CN4 - 8 LAP 20J - 20 PLCC Operation Range Industrial (-40 C to 85 C)
Package Type 8CN4 20J 44A 8-lead, 6 mm x 6 mm x 1.04 mm, Leadless Array Package (LAP) - Pin-compatible with 8-lead SOIC/VOIC Packages 20-lead, Plastic J-leaded Chip Carrier (PLCC) 44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
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20. Packaging Information
20.1 8CN4 - LAP
Marked Pin1 Indentifier
E
D
A A1
Top View
L1
8 1
Side View
Pin1 Corner
0.10 mm TYP
e
7 2
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A
6 3
MIN 0.94 0.30 0.45 5.89 5.89
NOM 1.04 0.34 0.50 5.99 5.99 1.27 BSC 1.10 REF
MAX 1.14 0.38 0.55 6.09 6.09
NOTE
A1
b
5 4
b D E e e1 L L1
1
e1
L
Bottom View
Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. Ni: 0.0005 to 0.015 mm Au: 0.0005 to 0.001 mm
0.95 1.25
1.00 1.30
1.05 1.35
1 1
2/15/08 Package Drawing Contact: packagedrawings@atmel.com TITLE 8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27mm, Leadless Array Package (LAP) GPC DMH DRAWING NO. 8CN4 REV. D
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AT17F16
20.2 20J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45
0.318(0.0125) 0.191(0.0075)
e E1 B E B1 D2/E2
D1 D A
A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 9.779 8.890 9.779 8.890 7.366 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 10.033 9.042 10.033 9.042 8.382 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 20J REV. B
R
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20.3
44A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
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21. Revision History
Revision Level - Release Date D - March 2006 E - August 2007 History Added last-time buy for AT17F16-30CC and AT17F16-30CI. Removed -30CC and -30CI devices from ordering information. Announced last-time buy for -30JC, -30BJC, -30JI, and -30BJI devices. Removed -30JC, -30JI, -30BJC and -30BJI devices from ordering information.
F - February 2008
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Headquarters
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
International
Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Product Contact
Web Site www.atmel.com Technical Support configurator@atmel.com Sales Contact www.atmel.com/contacts
Literature Requests www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
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